Optimal resistor network layout
US6060760A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1997 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Aug 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
Abstract
A resistor network having a precise ratio of resistances of all resistors within the network while having a compact layout to minimize area is described. The integrated circuit resistor network has a plurality of unit resistors. Each unit resistor is composed of a thin film resistive material. The area of the thin film resistive material to form the unit resistor is a median value of the resistor elements to be formed into said integrated circuit resistor network. Each unit resistor has a contact means to connect to the plurality of unit resistors. A plurality of metal interconnection segments will connect to the contact means to form said integrated circuit resistor network. A plurality of metal conductive segments are connected to a metal interconnection segments and to external circuitry to connect the external circuitry to the integrated circuit resistor network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.