High speed strobed comparator circuit having a latch circuit
US6060912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Sep 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A strobed comparator circuit with reduced signal propagation time has a regenerative latch in which, during the reset phase of operation, its output nodes are discharged to a common potential which is close to the regenerative voltage level of the cross-coupled transistors forming such regenerative latch rather than to circuit ground. Accordingly, overall signal propagation time is reduced by the amount of reduction in charging time necessary for one of the discharged nodes to recharge above the threshold voltage of one of the cross-coupled latch transistors. Also included is an output monitoring circuit which determines whether the regenerative latch has remained in a metastable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.