CMOS output stage for providing stable quiescent current
US6060940A · kind A · utility
7Cited by
11References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS output stage for providing stable quiescent current. The output stage includes a circuit that relates the quiescent current to the channel geometry of a power NMOS transistor and of an NMOS reference transistor of a reference current source. This configuration removes the dependency of the quiescent current on a power PMOS transistor used in the CMOS output stage, the threshold voltage of which may drift over time under high current and voltage operation, and adversely affects quiescent current stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.