Delay circuit for analog signals
US6061279A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1999 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Mar 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay circuit is provided, which is capable of eliminating the influence of noise of low frequency as disturbance. A plurality of memory cells including a plurality of capacitors store an analog signal as an input signal by storing charge of the input signal in the capacitors. A first inverting device inverts the input signal to generate an inverted signal. A control circuit generates and delivers control signals to the memory cells to select the input signal and the inverted signal alternately and sequentially write the selected signals into the memory cells in a predetermined writing sequence. The control circuit further generates and delivers to the memory cells to sequentially read out the input signal and the inverted signal from the memory cells in a sequence corresponding to the predetermined writing sequence. A second inverting device inverts the read-out inverted signal. An output signal is synthesized from the read-out input signal and an output signal of the second inverting device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.