Secure processor with external memory using block chaining and block re-ordering
US6061449A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1997 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Oct 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/7219
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scrambled data transmission is descrambled by communicating encrypted program information and authentication information between an external storage device and block buffers of a secure circuit. The program information is communicated in block chains to reduce the overhead of the authentication information. The program information is communicated a block at a time, or even a chain at a time, and stored temporarily in block buffers and a cache, then provided to a CPU to be processed. The blocks may be stored in the external storage device according to a scrambled address signal, and the bytes, blocks, and chains may be further randomly re-ordered and communicated to the block buffers non-sequentially to obfuscate the processing sequence of the program information. Program information may be also be communicated from the secure circuit to the external memory. The program information need not be encrypted but only authenticated for security.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.