Reconstruction engine for a hardware circuit emulator
US6061511A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and a method provide full visibility to each net of a design under modeling by saving states of the design during modeling and reconstructing waveforms at each net by logic evaluation using the saved states. In one embodiment, primary data input signals and memory output signals ("sample signals") are saved by a logic analyzer, and used in an emulator to generate state vectors from a state snapshot previously recorded. Data compression techniques can be applied to minimize storage requirements, and parallel evaluation of segments of waveforms can be achieved, since saved states for the entire period of interest are available for waveform reconstruction at the time of the logic evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.