Power and area efficient fast fourier transform processor
US6061705A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast Fourier transform (FFT) processor is constructed using discrete Fourier transform (DFT) butterfly modules having, in preferred example embodiments, sizes greater than 4. In a first example embodiment, the FFT processor employs size-8 butterflies. In a second example embodiment, the FFT processor employs size-16 butterflies. In addition, low power, fixed coefficient multipliers are employed to perform nontrivial twiddle factor multiplications in each butterfly module. The number of different, nontrivial twiddle factor multipliers is reduced by separating trivial and nontrivial twiddle factors and by taking advantage of twiddle factor symmetries in the complex plane and/or twiddle factor decomposition. In accordance with these and other factors, the present invention permits construction of an FFT processor with minimal power and IC chip surface area consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.