Method and apparatus for generating an end-around carry in a floating-point pipeline within a computer system
US6061707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Jan 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for generating an end-around carry to an end-around carry adder in a floating-point pipeline within a computer system is disclosed. The apparatus for generating an end-around carry includes a shift-comparison logic circuit, a sign-comparison circuit, and a logic gate. The shift-comparison logic circuit produces a shift-count signal and the sign-comparison logic circuit produces an effective operation signal. Coupled to the shift-comparison logic circuit and the sign-comparison logic circuit, the logic gate combines the shift-count signal and the effective operation signal with a carry-out signal generated by an end-around carry adder to provide an end-around carry signal for the end-around carry adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.