Patent · US Expired

Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions

US6061764A · kind A · utility

11Cited by

7References

12Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Suresh Chittor · Beaverton, US
Chih-Cheh Chen · Hillsboro, US
Sin S. Tan · Portland, US
Jonathan Spitz · Leonberg, DE

Key dates

Filing date	Jan 26, 1998
Grant date	May 9, 2000
Priority date	—
Expiry date	Jan 26, 2018

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0886
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.