Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub- 0.05 micron mosfets
US6063699A · kind A · utility
10Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30621
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a process of fabricating high aspect ratio holes (H/L is 2 or greater) in a semiconductor structure wherein a masked gate-like reactive ion etch process is employed. The high aspect ratio holes have perfectly vertical sidewalls thus they are particularly useful in fabricating gate electrodes of sub-0.05 .mu.m MOSFETs using a damascene process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.