Protection circuit with clamping feature for semiconductor device
US6064093A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1997 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Mar 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
In order to protect an internal circuit from high voltages caused by static electricity applied to a pad of a semiconductor device, a protection circuit is configured of a clamping circuit portion (6) utilizing a MISFET (5) connected between the pad (10) and the internal circuit (3) and a gate circuit portion (8) connected to the clamping circuit portion (6). The source and bulk terminals of the MISFET (5) of the clamping circuit portion (6) are connected to the pad (10) and the internal circuit (3), the drain thereof is connected to a first power supply terminal (11), the gate thereof is connected to one terminal of a gate circuit resistor (15) and one terminal of a capacitor (16) constituting the gate circuit portion (8), the other terminal of the gate circuit resistor (15) is connected to a second power supply terminal (12), and the other terminal of the capacitor (16) is connected to the first power supply terminal (11). As a result, surge voltages of positive and negative polarity caused by static electricity can be clamped at a low voltage by a single clamping element (MISFET) per pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.