Voltage regulator compensation circuit and method
US6064187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1999 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/565
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.