Low leakage circuit configuration for MOSFET circuits
US6064223A · kind A · utility
15Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Jul 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit configured with MOSFETs having a first range of subthreshold conduction, is provided with at least one switchable pathway between the circuit and a power or ground node, such that the switchable pathway is operable to substantially reduce leakage current through the circuit. In a further aspect of the present invention, the switchable pathway is a FET having substantially the same subthreshold conduction characteristics as the FETs in the circuit to which the switchable pathway is coupled, the FET being configured to be driven into both inversion and accumulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.