Multiple stage self-biasing RF transistor circuit
US6064253A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Apr 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/604
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
First and second spaced-apart planar circuit ground conductors are formed on a base substrate. Multiple stages of an amplifier each have a field effect transistor (FET) flip mounted onto the substrate. A signal-return line couples the sources of the FETs together and functions as a radio frequency (RF) grounds for the amplifier. Direct-current-blocking coplanar couplers couple the amplifier input and output to external circuits. A single voltage supply applies a bias voltage to the drains of the FETs. A source resistance device couples each source terminal to circuit ground. The source resistance devices may be formed of two series-connected resistors. The gate of each FET is coupled to one of the circuit ground conductors through one of the source resistors. The other source resistor thereby provides a gate-to-source voltage for biasing the FET. Alternative embodiments provide a community bias circuit in which signal-return lines of transistors conducting different signals are interconnected and coupled to the bias circuit ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.