Suppression of noise between phase lock loops in a selective call receiver and method therefor
US6064869A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Mar 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2215/064
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.