Method and apparatus for coalescing I/O interrupts that efficiently balances performance and latency
US6065089A · kind A · utility
68Cited by
7References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for generating an interrupt signal. A counter value is decremented each time a task is completed by a slave processor. The counter value is incremented each time a task is read by the slave processor. A delay value is set using the counter value. An interrupt is generated after a period of time set by the delay value has passed. The counter value is compared to a threshold value. The interrupt is generated upon detecting a condition in which the counter value is less than the threshold value or when the completion queue is full instead of after the period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.