Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing
US6065106A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. During emulation, the fetching of instructions from program memory can be halted. A packet of instructions can be transferred from the emulation unit to the instruction register of the processor via a test port and executed without fetching instructions from instruction memory. The packet of instructions can perform various tasks, such as loading or storing data or loading new instructions into program memory. Emulation…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.