Multi-speed DSP kernel and clock mechanism
US6065131A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1997 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Nov 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.