Information processing system having a CPU for controlling access timings of separate memory and I/O buses
US6065132A · kind A · utility
16Cited by
31References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | May 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an information processing system, a wait state signal is inserted into a RDY signal, according to which data are transmitted through memory and I/O buses. A CPU controls the number of the wait state signal to adjust the difference of the transfer speeds of the memory and I/O buses. An MCU (Memory Controller Unit) includes configuration and refresh timer registers for specifying the configuration and the refresh cycle of a memory to be accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.