Testing unit with testing information divided into redundancy-free information and redundancy information
US6065144A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit for applying a testing data to a DUT for testing the DUT comprises a buffer memory for receiving and buffering a redundancy-free information as information which is substantially free of redundancy but might also comprise some redundant information to a certain extent, a redundancy memory for storing a redundancy information as information comprising a certain amount of redundancy, and a processing unit for generating the testing data by processing the redundancy-free information in association with the redundancy information. Further, includes a method for applying a testing data to the DUT for testing the DUT includes the steps of receiving and buffering the redundancy-free information, fetching in accordance with the received redundancy-free information the redundancy information, and generating the testing data by processing the redundancy-free information in association with the redundancy information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.