Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process

US6066525A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Yauh-Ching Liu · Boise, US
• Ruggero Castagnetti · Menlo Park, US
• Subramanian Ramesh · Milwaukee, US

Key dates

• Filing date: Aug 2, 1999
• Grant date: May 23, 2000
• Expiry date: Aug 2, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/30

Abstract

Disclosed are planar DRAM cells including a storage capacitor having a high dielectric constant capacitor dielectric. The DRAM cell also includes an access transistor having a gate dielectric which does not include the high dielectric constant material. A single polysilicon layer is employed to form the gate electrode of the access transistor and a reference plate of the storage capacitor. A disclosed fabrication process forms the high dielectric constant material that is limited to a capacitor region of the DRAM cell and then forms the gate dielectric over an entire active region including both the high dielectric constant material layer at the capacitor region and the semiconductor substrate at the access transistor region. In this manner, a high quality gate dielectric (e.g., silicon oxide) is formed at the access transistor region and a high dielectric constant dielectric layer (e.g., silicon nitride) is formed at the capacitor region. A capacitor plate and a gate electrode are formed by patterning the same conductive layer (e.g., doped polysilicon) formed over top of the gate dielectric.