Programmable logic device having combinational logic at inputs to logic elements within logic array blocks
US6066960A · kind A · utility
102Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | May 21, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
AND gates are used at the inputs to logic elements in a programmable logic device. This allows more efficient configuration of the logic elements for basic functions such as a multiplier, clearable counter and multiplexer. Inputs to the AND gates are enabled by LAB-wide control signals that are distributed to several logic elements within a logic array block. The control signals can also be generated from a RAM or ROM, or by decoding existing control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.