Differential receiver with duty cycle asymmetry correction
US6066972A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for correcting asymmetry in the duty cycle of a differential signal is disclosed. The differential receiver circuit includes a first converter including a positive input coupled to a first direct current (DC) blocking capacitor, a negative input coupled to a second DC blocking capacitor, and an output resistively coupled to the positive input of the first converter. The differential receiver circuit further includes a second converter including a positive input coupled to the negative input of the first converter, a negative input coupled to the positive input of the first converter, and an output resistively coupled to the negative input of the first converter. The respective outputs of the first and second converters are preferably inverting outputs. A differential output signal having a duty cycle of approximately 50 percent is produced between respective outputs of the first and second converters in response to a differential input signal having a duty cycle greater than or less than 50 percent. The first and second converters may be respectively implemented as low level differential-to-CMOS converters. The first and second DC blocking capacitors and res…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.