Patent · US Expired

SRAM memory cell

US6067247A · kind A · utility

1Cited by

2References

9Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Harald Gossner · Riemerling, DE
Ignaz Eisele · Icking, DE
Franz Wittmann · Hockenheim, DE
Rao Valipe Ramgopal · Hersbruck, DE

Key dates

Filing date	Mar 23, 1998
Grant date	May 23, 2000
Priority date	—
Expiry date	Mar 23, 2018

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/40
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A three-transistor SRAM memory cell includes a bistable field-effect transistor having a fully depleted floating channel region and a hysteretic gate voltage characteristic curve. The bistable field-effect transistor has a gate to be connected to a first bit line for the purpose of writing to the memory cell and a second channel terminal to be connected to a second bit line for the purpose of reading from the memory cell. The two bit lines can be identical. The connection between the bit lines and the bistable transistor can be effected through first and second respective transistors which are each controlled by a respective word line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.