Static semiconductor memory device operating at high speed under lower power supply voltage
US6067256A · kind A · utility
42Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 5, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | May 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line load element for reducing a bit line amplitude during data reading is formed of p- and n-channel MOS transistors connected in parallel. When a word line is driven to the selected state, the p-channel MOS transistor is held off. In the data write operation, both the n- and p-channel MOS transistors are turned off. Even under a low power supply voltage, a sufficiently large bit line amplitude can be produced without an influence by a size of the bit line load element. By deactivating the bit line load element in the data write operation, it is possible to prevent generation of a DC current during data writing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.