Frequency divider with lower power consumption

US6067339A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Herbert Knapp · Munich, DE
• Wilhelm Wilhelm · Munich, DE

Key dates

• Filing date: Sep 15, 1998
• Grant date: May 23, 2000
• Expiry date: Sep 15, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K23/667
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A frequency divider such as a dual modulus prescaler has a division factor switchable between 1/N and 1/(N+1) and an input frequency of approximately 1 GHz as occurs, for example, in mobile telecommunication systems (GSM or DECT telephones). Low power consumption is achieved by using only the input flipflop to process the relatively high input frequency and an intermediate signal having only half the frequency is supplied to an intermediate divider and an output signal is already taken at a penultimate stage of a divider expansion connected following the intermediate divider.