Method and apparatus for avoidance of invalid transactions in a bus host controller
US6067591A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Oct 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for ensuring frame integrity in a bus system are disclosed. In the disclosed system, each scheduled transaction is evaluated before execution to determine whether there is enough time in the frame to complete the transaction. By separately evaluating each transaction at the time of execution, held off transactions are not aborted if the frame ends before the transaction completes. Each transaction is evaluated by determining the approximate length of the transaction and comparing the approximate length to the number of byte times remaining in the frame. A step function is used to determine the approximate length by adding one of two possible constant values which take into account transaction overhead to the number of data bytes in the transaction, the selected constant value being dependent upon the number of data bytes, a smaller constant value being added for smaller transactions and a larger transaction value being added for larger transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.