Reconfigurable processor for executing successive function sequences in a processor operation
US6067615A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1995 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Nov 9, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor with reconfigurable architecture includes a processor input and a processor output. A library stores a plurality of related function sequences for executing a processor operation. Memory stores data as required by the function sequences. A configurable device is connected to the library and the memory and between the processor input and the processor output. The configurable device sequentially stores the function sequences from the library in a plurality of programmable gate arrays configurable by the function sequences. The configurable device reconfigures the programmable gate arrays with another of the function sequences to complete the processor operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.