System and method monitoring instruction progress within a processor
US6067644A · kind A · utility
34Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Apr 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.