Method for forming diffusion barrier layers
US6069073A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Jul 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76855
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved method for forming diffusion barrier layers for sub-micron connects in integrated circuits is disclosed. The dual diffusion barriers is easily formed according to two-step annealing processes. The anneal includes two anneal cycles or steps, each cycle is performed at a separate and distinct temperature cycles. Each cycle is performed in the presence of ammonia (NH3) or nitrogen ambient. As a result of the first low-temperature cycle, a nitridation occurs at the upper surface to form a binary diffusion barrier layer. As a result of the second high-temperature cycle, an out-diffusion of silicon ions occurs at the lower surface to form a ternary alloys. The dual diffusion barriers obtained by a simple and easy two-step anneal processing exhibits an improved barrier performance. Furthermore, it is possible to form highly stable multilevel interconnections without any deterioration problems by reducing the sophisticated processing steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.