Clock generator for CMOS circuits with dynamic registers

US6069498A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Tobias Noll · Neckartailfingen, DE
• Stefan Meier · Neubiberg, DE
• Matthias Schobinger · Hersbruck, DE
• Erik De Man · Hersbruck, DE

Key dates

• Filing date: Nov 5, 1997
• Grant date: May 30, 2000
• Expiry date: Nov 5, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/19
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.