Digital slew rate and duty cycle control circuit and method
US6069511A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal shaping circuit for use in a transmission line driver and the like is disclosed. The input is pulse signal having a rising edge that triggers a delay circuit which produces a first sequence of multiple delayed outputs and a falling edge which triggers the delay circuit to produce a second sequence of multiple delayed outputs. Transition control circuitry is included which operates to control the transition time of the output signal in a first direction, such as the rise time, in response to the first sequence of multiple delayed outputs and to control the transition time of the output signal in a second direction, such as the fall time, in response to the second sequence of multiple delayed outputs. By controlling the first and second delayed output, the rise and fall times of the output signal can be precisely controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.