Toggle flip-flop network with a reduced integration area
US6069513A · kind A · utility
1Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Aug 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A toggle flip-flop with reduced integration area, comprising a flip-flop of the D-type with an inverting input stage and a master-slave portion. Three transistors connected to the inverting stage form a logic gate of the XOR type whereto the output terminal of the master-slave portion is fed back.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.