Voltage regulation method for attenuating inductance-induced on-chip supply variations
US6069521A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines. The structures and methods are useful on a power supply board to attenuate periodic ripple voltages produced by a DC-DC converter. In general, the structures and methods are …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.