Hadamard code generation circuit
US6069574A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 24, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Aug 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/707
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A hadamard code generation circuit is disclosed. The circuit includes a start reset signal generator for generating a start reset signal START.sub.-- RESET when a 6-bit output signal REF.sub.-- C from the 6-bit reference counter, a higher 4-bit index output signal H(5:2) of the 6-bit register and a 2-bit value from a ground circuit are identical; a "0" value force allocation unit for outputting a FORCE.sub.-- 0.sub.-- DEL signal for forcibly allocating all values of the 0th column to "0" when a 4-bit output signal REF.sub.-- C (5:2) from the 6-bit reference counter and a 4-bit value from the ground circuit are identical; a 2-bit counter for receiving the start reset signal and an external clock signal, outputting lowest bit signals C1 and C0 and outputting a carry-out signal; a 4-bit counter operated in accordance with a result that an inverted FORCE.sub.-- 0 signal and a carry-out signal are ANDed and outputting higher bit signals C4, C3 and C2; a 4th hadamard code generator for logically processing a lower 2-bit output signal from the 2-bit counter and a lower 2-bit index value from the 6-bit register and generating a 4-th hadamard code; a 12th paley code generator for generating…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.