High-speed responding data storing device for maintaining stored data without power supply
US6069816A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Nov 24, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is an object of the present invention to provide a data storing device capable of responding in high speed without providing a power supply just for maintaining the stored data. A memory cell MC11 is made so as to replace only a memory transistor MT1 out of a pair of memory transistors MT1 and MT2 used for the prior art SRAM with a transistor with "MFMIS structure" having a ferroelectric layer 32. The ferroelectric layer 32 keep storing a polarization state in response to ON state stored in the memory transistor MT1 even when a power supply of the device is turned off. The memory transistor MT1 is turned into ON state in accordance with the polarization state stored in the ferroelectric layer 32 when the power supply is turned on again. In response to the change in state at the memory transistor MT1, the memory transistor MT2 is turned into OFF state. That is, the memory cell MC11 is defined as a ferroelectric memory. In addition, the reversal of the polarity in the ferroelectric layer 32 is carried out in high-speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.