Memory system
US6069827A · kind A · utility
187Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 24, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Mar 24, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid state memory for emulating a disk drive comprising: translation means for translating a logical sector address to a main memory address; a main memory composed of non-volatile memory cells erasable in blocks; characterized in that a first pointer is used to point to an unwritten location in main memory, and a second pointer is used to point to the next unerased erasable block in sequence to the erasable block containing the said unwritten memory location; control means being provided to ensure that there is always at least one erasable block in the erased condition between the first and second pointers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.