Row decoder circuit for an electronic memory device, particularly for low voltage applications
US6069837A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Dec 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, is described. The row decoding circuit is adapted to boost, through at least one boost capacitor, a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference and a second ground potential reference, and comprises a hierarchic structure of cascade connected inverters and a circuit means of progressively raising the read voltage level dynamically. First means are provided for raising the read voltage level to a value equal to the supply voltage plus a threshold voltage, and second means are provided for raising the read voltage level to a value equal to the supply voltage plus twice said threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.