Host adapter having paged data buffers for continuously transferring data between a system bus and a peripheral bus
US6070200A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Jun 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/122
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses one page to hold data that is currently being received, while using another page containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g. peripheral device address, or system memory ad…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.