Interrupt capture and hold mechanism
US6070218A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Jan 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.