Method of manufacturing CMOS image sensor leakage free with double layer spacer
US6071826A · kind A · utility
30Cited by
6References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1999 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/80
Abstract
A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.