Method of fabricating semiconductor components
US6071829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/26
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of fabricating a semiconductor component, the method including at least one step of etching an upper layer formed on a substrate. In the method, prior to forming the upper layer, at least one set made up of marker layers separated by intermediate layers of predetermined thicknesses is caused to be grown, where the marker layers and adjacent intermediate layers have different refractive indices, and then during etching of the upper layer refractive index discontinuities are detected optically and etching is stopped when the sequence of the optically detected discontinuities corresponds to a reference sequence representative of the thicknesses of the intermediate layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.