Solid state image sensor
US6072206A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1999 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Mar 19, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/50
Abstract
The present invention provides a solid state image sensor constructed in such a manner that, even if the impurity concentration of the wells of a transistors is increased, the junction leakage current does not increase, and thus, the picture quality of the reproduced picture is not deteriorated. On a p-type substrate, there are formed a first p-type well for a photoelectric conversion portion comprising a photodiode, and a second p-type well for a signal scanning circuit portion. In the surface portions of the first and second p-type wells, a first and a second n-type diffused layers are formed, respectively. The drain of a reset transistor and the drain of an amplifying transistor which constitute the second n-type diffused layer are connected to a power supply line. Further, the source of an address transistor which is an n-type diffused layer is connected to a vertical signal line. The gates of the amplifying transistor and the address transistor are formed between second n-type diffused layers disposed at predetermined intervals on the surface of the second p-type well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.