Method and apparatus for sigma-delta demodulator with aperiodic data
US6072843A · kind A · utility
6Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Jan 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.