Patent · US Expired

Bit-serial linear interpolator with sliced output

US6073151A · kind A · utility

9Cited by

6References

22Claims

0Family size

Assignee

Motorola, Inc. · US

Inventors

James C. Baker · Bartlett, US
Denise Carol Riemer · Gurnee, US
John P. Oliver · Memphis, US

Key dates

Filing date	Jun 29, 1998
Grant date	Jun 6, 2000
Priority date	—
Expiry date	Jun 29, 2018

Classification

Technology area (CPC H)Electricity
CPC primaryH03H17/0657
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.