Low speed serial bus protocol and circuitry
US6073186A · kind A · utility
16Cited by
14References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Feb 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4295
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial bus communications method and circuitry for low speed serial bus functions. Over a two-wire communications channel, a unidirectional clock line and a bidirectional data line are used to transfer data. A protocol defines permissions, acknowledgments, terminations and retries handshaking between points. Circuitry is provided for reducing the latency of the serial bus when cooperating with the low speed functions. A resistive connection scheme is disclosed for converting high voltage signals into lower voltage signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.