System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
US6073190A · kind A · utility
151Cited by
20References
41Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Jul 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.