System and method for minimizing page tables in virtual memory systems
US6073226A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Mar 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention described herein works in conjunction with a processor having an address translation cache that is updated by referencing a page table directory and a plurality of associated page tables referenced by the page table directory. The page table directory and a single page table are configured to generate a memory fault whenever the processor attempts to update its address translation cache. In response to such a memory fault, a memory fault handler temporarily loads a single page table entry with the needed address translation. In addition, the memory fault handler initializes the page table directory so that it references the single page table entry that has been loaded. Control is then returned from the memory fault handler, and the processor obtains the address translation. In response to a subsequent memory fault, the memory fault handler invalidates the previously loaded entry, and loads whatever address translation is currently needed by the processor. The address translations are cached in the processor's translation lookaside buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.