Modulo address generator for generating an updated address
US6073228A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Sep 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modulo address generation circuit for generating multiple-word memory accesses for use in a computer system. The circuit includes an address pointer latch for retaining a current address pointer, an adder for receiving the current address pointer as a first input and a displacement as a second input. The adder for adding the inputs to provide an output. A comparator compares the current address pointer to an ending address of a circular buffer ignoring least significant bits thereof when the displacement is greater than one. The comparator provides an output that is a first state when the inputs are the same and an output that is a second state when the outputs are different. A control circuit is adapted to receive an indicator of the beginning address of the circular buffer, an indicator of the current address pointer, and an indicator of the ending address of the circular buffer. The control circuit provides the output of the adder to the address pointer latch as an updated address pointer when the indicators take on predetermined values and the comparator output is in the second state. The control circuit provides the beginning address to the address pointer latch as an update…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.