Information processing system
US6073249A · kind A · utility
16Cited by
17References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Aug 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.